101 lines
3.9 KiB
Python
101 lines
3.9 KiB
Python
"""
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CAP, SSA Intro, Elimination and Optimisations
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Functions to convert a CFG out of SSA Form.
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"""
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from typing import cast, List, Set, Tuple
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from Lib.Errors import MiniCInternalError
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from Lib import RiscV
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from Lib.Graphes import DiGraph
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from Lib.CFG import Block, BlockInstr, CFG
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from Lib.Operands import (
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Register, DataLocation,
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Temporary, TemporaryPool)
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from Lib.Statement import AbsoluteJump
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from Lib.Terminator import BranchingTerminator, Return
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from Lib.PhiNode import PhiNode
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from TP05.SequentializeMoves import sequentialize_moves
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def generate_moves_from_phis(phis: List[PhiNode], parent: Block) -> List[BlockInstr]:
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"""
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`generate_moves_from_phis(phis, parent)` builds a list of move instructions
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to be inserted in a new block between `parent` and the block with phi nodes
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`phis`.
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This is an helper function called during SSA exit.
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"""
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moves: List[BlockInstr] = []
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plabel = parent.get_label()
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for phi in phis:
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if(plabel in phi.used()):
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moves.append(RiscV.mv(phi.var,phi.used()[plabel]))
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return moves
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def generate_moves_from_phis_smart(pool: TemporaryPool, phis: List[PhiNode], parent: Block) -> List[BlockInstr]:
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"""
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`generate_moves_from_phis_smart(phis, parent)` builds a list of move instructions
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to be inserted in a new block between `parent` and the block with phi nodes
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`phis`. This function is working with smart allocation, unlike its «dump» counterpart
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that makes allocations in no particular order.
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This is an helper function called during SSA exit.
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"""
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moves: List[Tuple[DataLocation,DataLocation]] = []
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plabel = parent.get_label()
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for phi in phis:
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if(plabel in phi.used()):
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src = phi.var
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dest = phi.used()[plabel]
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if(isinstance(src,Temporary)):
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src = pool.get_alloced_loc(src)
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if(isinstance(dest,Temporary)):
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dest = pool.get_alloced_loc(dest)
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assert(isinstance(dest,DataLocation))
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moves.append((dest,src))
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realmoves = sequentialize_moves(set(moves))
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return realmoves
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def exit_ssa(cfg: CFG, is_smart: bool) -> None:
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"""
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`exit_ssa(cfg)` replaces phi nodes with move instructions to exit SSA form.
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`is_smart` is set to true when smart register allocation is enabled (Lab 5b).
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"""
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for b in cfg.get_blocks():
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phis = cast(List[PhiNode], b._phis) # Use cast for Pyright
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b._phis = [] # Remove all phi nodes in the block
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blabel = b.get_label()
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parents: List[Block] = b.get_in().copy() # Copy as we modify it by adding blocks
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for p in parents:
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moves = generate_moves_from_phis_smart(cfg.fdata._pool,phis, p) if is_smart else generate_moves_from_phis(phis, p)
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if(len(moves)==0):
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continue
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# Creating the block
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ilabel = cfg.fdata.fresh_label(p.get_label().name+"_to_"+b.get_label().name)
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i = Block(ilabel,moves,AbsoluteJump(blabel))
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# Add the block
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cfg.add_block(i)
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# Changing the jumps
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ot = p.get_terminator()
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if(isinstance(ot,BranchingTerminator)):
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if(ot.label_then == blabel):
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ot.label_then = ilabel
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if(ot.label_else == blabel):
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ot.label_else = ilabel
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elif(isinstance(ot,AbsoluteJump)):
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assert(ot.label == blabel)
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ot = AbsoluteJump(ilabel)
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elif(isinstance(ot,Return)):
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raise MiniCInternalError("Malformed CFG, cannot have a return in a parent block")
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else:
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raise MiniCInternalError("I don't know of this terminator type:",type(ot))
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p.set_terminator(ot) # This instruction might be useless
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# Moving from p -> b to p -> i -> b
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cfg.remove_edge(p,b)
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cfg.add_edge(p,i)
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cfg.add_edge(i,b)
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