Upgraded circuit generation

This commit is contained in:
2024-05-20 01:02:42 +02:00
parent ef8b8910b0
commit 0298b85323
6 changed files with 62 additions and 25 deletions
+14
View File
@@ -37,6 +37,20 @@ logikraft.components = {
left = {nil,nil,nil,nil,nil,"in_3","in_2","in_1"},
right = {"out_8","out_7","out_6","out_5","out_4","out_3","out_2","out_1"}
}
},
["input"] = {
width = 1,
height = 1,
ports = {
right = {"out"}
}
},
["output"] = {
width = 1,
height = 1,
ports = {
left = {"in"}
}
}
}
-11
View File
@@ -1,11 +0,0 @@
minetest.register_node("logikraft:inputBlock", {
description = "Input Block",
tiles = {"input_block.png"},
groups = {circuitry = 1,dig_immediate = 3}
})
minetest.register_node("logikraft:outputBlock", {
description = "Output Block",
tiles = {"output_block.png"},
groups = {circuitry = 1,dig_immediate = 3}
})